Designed to support the next generation of high speed, low latency extremely high bandwidth random access memory applications.
Quazar Family Target Goals
Today, systems are more complex. Bandwidth has increased tremendously. Gone is the reliance on single device specification. Data and information flow require a System Memory Strategy that involves the tradeoffs of DRAM, SRAM and FPGA memory. Memory designs must be thought as part of the system and not only at the component level. For memories today, the decision points are:- Access time
- Random-access flexibility
- System latency
- Along with cost
The QUAZAR family of memories were designed to take the best of the QDR type devices and add capabilities to accelerate applications at the SYSTEM level.
QUAZAR Device – QPR4 and QPR8
The Quazar family is specifically designed to support the next generation of high-speed, low latency extremely high bandwidth random access memory applications. The QPR devices are x4 or x8 the capacity of the most common QDR SRAM devices which operate at approximately one eighth to one-quarter of the QPR bandwidth.
Total QPR Solutions has Three System Elements
MoSys defined the QPR memory as a solution product, with the goal of providing a simple path to upgrade designs from QDR with higher capacity but with a less design effort and minimal impact on software.
- MoSys supplied RTL Memory Controller
- QDR type RTL interface
- Provides RTL 72b registers
- Instruction/Data registers to memory
- Data registers from memory
- Support user selectable work widths
- Up to 576b
- Controls the SerDes protocol (transparent to user)
- SerDes high speed Memory/FPGA interface
- Most FPGAs have multiple SerDes lines
- QPR4 device available with 10 Gb/s or 12.5 Gb/s
- QPR8 devices available with 15 Gb/s or 25 Gb/s
- Lowest pin count interface…minimum of 8 FPGA pins
- Typical of 32 pins
- Preferred FPGA today and future interface direction
- QPR (Quad Partition Rate) memory Architecture
- Memory architecture with Partitions divided into Banks
- Each partition is accessed like an independent SRAM
- Bandwidth determined by user
QPR Family Comparison vs. QDR
- Memory size
- 4x to 8x common QDR
- Device PCB board space saving
- 1 device vs 4 or 8 QDR
- Signal pin reductions
- 4 QDRs: 500-720 pins
- 8 QDRs: 1072-1440
- 1 QPR4 OR QPR8: typical system 32 pins
- All MoSys devices have Auto-Adaptation which handles on-board signal tuning, eliminating the need for any external components to ensure clean, reliable signals
- Cost
- One QPR4 with 4x the memory capacity is generally less than the price of 2 QDR memories
- One QPR8 with 8x the memory capacity is about 3 QDR memories
- Applications
- Larger buffers, High Bandwidth networking applications like search tables
- Allows real time operations and analysis at line or data rates
- Eliminates need for complex parallel
- operations using RLDRAM, HBM, or slow DRAM
- LOW COST
- 60-70% Less Costs than the equivalent QDR configuration
- Base Product: High Volume price of <$200
- Provide high capacity
- 576Mb and 1Gb
- Fully random access to all memory locations
- Independent random-access partitions with simultaneous access
- Low tRC
- 2.6ns and 3.2ns
- Higher bandwidth
- 360 Gb/s
- Low power
- Less than half QDR
- MoSys RTL Controller with simplified QDR like register interface
- Equal or better performance than a QDR at a system level
- Up to 576 b word width